Modeling simulation and analysis of double gate heterojunction tunnel fet for analog and low power applications

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dc.contributor.guideArun Samuel, T S
dc.coverage.spatialModeling simulation and analysis of double gate heterojunction tunnel fet for analog and low power applications
dc.creator.researcherJeyanthi, J E
dc.date.accessioned2025-11-21T04:17:49Z
dc.date.available2025-11-21T04:17:49Z
dc.date.awarded2025
dc.date.completed2025
dc.date.registered
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions21cm
dc.format.extentxix,141p.
dc.identifier.researcherid
dc.identifier.urihttp://hdl.handle.net/10603/675289
dc.languageEnglish
dc.publisher.institutionFaculty of Electrical Engineering
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.relationp.116-140
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordheterojunction
dc.subject.keywordsemiconductor devices
dc.titleModeling simulation and analysis of double gate heterojunction tunnel fet for analog and low power applications
dc.title.alternative
dc.type.degreePh.D.

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