Design Synthesis and Implementation of Video Codec

Abstract

newline In the past few decades, there is a drastic improvement in the communication due to newlineadvanced technologies and algorithms to make channel or media error free without newlinecongestion. In this era, the bandwidth is limited for the transmission of data particularly biosignals newlineand video signals through wired/wireless channels/media. The oldest communications newlinewere lagging from transmission of video signals which require higher bandwidth. To address newlinethese challenges, the proposed research work mainly concentrates on high efficiency video newlinecoding (HEVC) and it is latest video coding standard to meet challenges in the digital newlinemultimedia communication world. newlineThe current video standards suffer from compression of data to reduce the bandwidth newlinedue to lengthy computation techniques. Video codec needs to improve the compression speed newlinewithout deteriorating the performance parameters like video quality, PSNR and structural newlinesimilarity. The next challenge, in this research work is to address the limitations of DSP newlineprocessor. This research work is to suggest the improvement in the computation speed by newlineproposing suitable modifications in the existing DSP processor, the same is designed and newlineimplemented on FPGA by utilizing the vedic algorithms, multi-stage pipelined structure to newlineimprove the speed with optimized area and power dissipation. Further the work proposed a newlinevideo codec (Application specific DSP processor) i.e. HEVC/H.265, a modified version of newlineh.264 which performs better with respect to the all parameters. Xilinx 14.7 ISE and Vivado/ newlinechip scope-pro tools are used to test the efficiency of the proposed modification and newlinealgorithms newlineThe first phase of this research work, mainly concentrates on 64- bit DSP processor newlinedesign by incorporating optimized advanced operation like error correction algorithm called newlinebit wise error correction per symbol (BWECPS), floating point multipliers (as per IEEE 754 newlineformat), ALU, convolution, Encoder and decoder algorithm and advanced adder. The newlinecomplete 64 bit DSP processor has been designed