System design and prototyping of the CMS Level 1 Calorimeter trigger at the High Luminosity LHC

Abstract

The High-Luminosity LHC (HL-LHC) project offers a very ambitious physics program newlinethat includes high-precision measurements of the Standard Model (SM) and the searches newlinefor new physics beyond the SM (BSM). The efficient data collection and precise events newlinereconstruction in the harsh environment of 200 proton-proton interactions per bunch newlinecrossing are vital for achieving the success of the HL-LHC program. To fulfill these newlinerequirements, the CMS experiment plans to build and install completely new data acquisition newline(DAQ) and trigger systems during the so-called CMS Phase-2 upgrade. The newlinePhase-2 CMS Level-1 calorimeter trigger system will handle the enormous detector input newlinedata bandwidth of 75 Tbps and is desired to complete the single event processing within newline12.5 and#956;s. For this purpose, CMS plans to replace the Phase-1 and#956;TCA-based processor newlineboards and crates with an ATCA form factor. Each ATCA board will host Xilinx Ultra- newlineScale+ family FPGA that supports over a hundred high-speed optical links at 25 Gbps, newlinecapable of meeting the high bandwidth and processing requirements of the HL-LHC. newlineAlong with the advancement in hardware, the Level-1 trigger system will employ highly newlinemodular, flexible, and adequately sophisticated algorithms currently possible only in newlineoffline reconstruction, such as a particle-flow algorithm. The modular and flexible architecture newlinewill help to address the HL-LHC physics requirements. In this thesis, we will newlinediscuss the system design, prototyping, and algorithms being developed for the Phase-2 newlineLevel-1 Calorimeter trigger system. newline