Power management techniques for reliable network on chip

Abstract

newlineNetwork on Chip NoC is an effective solution for integrating all processing elements PE or Intellectual Property IP blocks on a single System On Chip SoC in VDSM Very Deep Sub Micron technology NoC has beneficial features like scalability resolve timing closure issues performance at higher operating frequencies and reusability of IP blocks; hence SoCs choose NoC IP interconnect fabric as a better alternative to traditional hierarchal bus based architecture With shrinking technology the size of SoC has become larger with higher complexity multi core and multicore architectures; hence current NoC face the challenge of achieving low power consumption by maintaining signal integrity and system reliability A conventional NoC consists of routers network interface and interconnection links As the technology scales down wires that form the links are more power hungry and consequently link power forms the dominant portion of communication in NoC The power consumption of the link depends on switching activity both self and coupled switching activity swing voltage and operating frequency Link power consumption can be reduced by lowering switching activity by suitable encoding method which is the traditional procedure followed It can also be reduced by lowering swing voltage but it may introduce performance degradation Communication reliability is a major challenge faced by NoCs in low swing signaling methodology as NoC is prone to transient multiple errors in transmitted bits To maintain low power reliable high speed on chip communication solutions that address low power consumption in on chip interconnection links and powerful error correcting codes are needed newline newline