Current Steering Digital to Analog Converters Architectures and Calibration Techniques

Abstract

The CMOS IC design requires an in-depth analysis to achieve the desired goal, that newlineis, small size, high speed, and high accuracy, considering the trade off between all these parameters. Because DACs are the major part of any application, such as medical newlineinstrument, industrial instrument, radio, mobile, and High Definition Television(HDTV), newlinedesigning a DAC of a small size and with less power consumption is essential. This newlinethesis shows modifications in the existing schemes as well as novelties in architecture newlineand calibration of current steering (CS) DACs. In this study, I have focused on the binary-weighted CS DAC architecture, instead newlineof the segmented architecture because of its advantages such as less area, low power newlineconsumption, and requirement for less number of control signals. The circuit was newlineimplemented in a state-of-the-art 180-nm CMOS process, with a supply voltage of 3 V newlineand at a sampling speed of 100MHz. newlineBased on extensive literature survey, a new architecture was designed to improve performance parameters. A novel current mirror architecture is proposed and was verified on a 6-bit CS DAC. Furthermore, sizing of transistors is a limiting factor for high resolution DACs, and the proposed architecture was unable to perform more satisfactorily, and thus different calibration techniques were studied. There are two basic types of calibration processes: foreground and background calibration. Background calibration process displays higher power dissipation and complexity in implementation; therefore, foreground calibration process (FGP) was adopted. The error might be processed digitally or analogy.The digital FGP requires successive approximation register(SAR), static random access memory (SRAM), calibration DAC (CALDAC), and complicated controller circuitry, whereas an analog FGP uses high speed op-amp and various capacitors.