Tunnel FET Based Topologies for Low Power Digital and Analog Circuits

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dc.contributor.guidePattanaik, Manisha
dc.coverage.spatial
dc.creator.researcherJha, Kamal Kishor
dc.date.accessioned2023-11-10T09:10:56Z
dc.date.available2023-11-10T09:10:56Z
dc.date.awarded2015
dc.date.completed2015
dc.date.registered2011
dc.description.abstractAttached
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions27.5X21.2
dc.format.extentxix,127p.
dc.identifier.urihttp://hdl.handle.net/10603/524769
dc.languageEnglish
dc.publisher.institutionDepartment of Electrical and Electronics Engineering
dc.publisher.placeGwalior
dc.publisher.universityAtal Bihari Vajpayee Indian Institute of Information Technology and Management
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleTunnel FET Based Topologies for Low Power Digital and Analog Circuits
dc.title.alternative
dc.type.degreePh.D.

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