Computational Geometry Analysis of ASIC Layouts and Defect Detection in Fabrication

dc.contributor.guide	Agarwal, Vineeta
dc.coverage.spatial
dc.creator.researcher	Abhishek Vikram
dc.date.accessioned	2023-02-06T06:35:35Z
dc.date.available	2023-02-06T06:35:35Z
dc.date.awarded	2016
dc.date.completed	2016
dc.date.registered	2010
dc.description.abstract	Available newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	i;117p.
dc.identifier.uri	http://hdl.handle.net/10603/456237
dc.language	English
dc.publisher.institution	Department of Electrical Engineering
dc.publisher.place	Allahabad
dc.publisher.university	Motilal Nehru National Institute of Technology
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Computational Geometry Analysis of ASIC Layouts and Defect Detection in Fabrication
dc.title.alternative
dc.type.degree	Ph.D.