Investigations on performance Improvements of self biased Adaptive bandwidth PLLS

Abstract

The present research work attempts a number of modifications of newlinethe well established self biased adaptive bandwidth Phase Locked Loop newline PLLs These modifications are considered in order to address the issues that newlinehave become important in the context of PLLs for multi core processors newlinewhich operate with progressively increasing speeds and reduced supply newlinevoltages In a multi core environment the processor clocks are switched newlinerapidly across different pairs of frequency and supply voltage settings in order newlineto maintain the lowest power envelope constraint This requirement newlinecombined with high operating frequencies thus demands faster settling times newlineaccompanied by lower jitter constraints on the PLL design Simultaneously newlinethe PLLs also feed increasing number of Delay Locked DLLs Loops and newlineclock networks hence the capture transients overshoot undershoot of these newlinePLL are required to be as minimum as possible Motivated by these evolving newlineConstraints the present work investigates alternative ways in which the newlinetraditional self biased PLL architecture can be modified to improve the newlineperformance with respect of jitter capture transients undershoot overshoot newlinesettling time and operating frequency range while retaining the inherent newlinebenefits of the traditional second order self biased adaptive bandwidth PLL newlinearchitecture To the best of this researcher s knowledge such studies of newlinerelative contributions to overall jitter or methods of their reduction have not newlinebeen reported in the literature in the context of self biased PLL s though newlinethese continue to be widely used for microprocessor clock generation newline newline