Performance studies of the dual loop clock and data recovery circuits in the presence of power supply noise

Abstract

Clock and Data Recovery circuits have been used extensively in the receivers of optical communication systems and even today their use are expanding rapidly to a variety of applications in inter and intra chip communications Increasing speeds of operation integration and miniaturization lower operating power supply and lower power dissipation are emerging as important issues that severely limit the architectural choices newlineFurther these choices also have to operate under more and more severe constraints of power supply noise process and temperature variations The present thesis investigates the impact of power supply noise on the jitter performance of dual loop architecture of CDR circuit proposed by Seema Butala Anand et al an architecture which is considered as one of the important alternatives available for implementing CDR circuits A systematic newlinesimulation study has been carried out to determine the power supply noise sensitivity of each individual block of the dual loop CDR circuit and the quantitative results obtained are presented in this thesis Simulation results indicate that this architecture is very sensitive to power supply noise and it is demonstrated that insertion of suitable Low Dropout Regulators is essential to enhance the performance of the CDR system with respect to power supply noise newline