Design and Analysis of Reliability Aware CMOS Circuits for a Neuromorphic System

Abstract

The current study proposes the implementation of SLIFMEM, a neuromorphic system newlineconsisting of programmable synaptic memory and neural core blocks. The SLIFMEM is newlineimplemented with SRAM as synaptic memory of size 1024 with 5-bits word. The SLIFMEM newlineneural core consists of DPI based SiS, and SLIF neuron. The present work also implement the newlinereliability-aware SLIFMEM, referred to as rel-SLIFMEM, which is developed by replacing SLIF newlineSiN with rel-SLIF SiN in its neural core. The impact of BTI and HCI on the performance of the newlinerel-SLIFMEM is analyzed using a key performance metric, inter-spike interval. The performance newlineof rel-SLIFMEM is compared with the conventional SLIFMEM. Finally, the energy consumption newlineof rel-SLIFMEM is examined at time-zero and compared with conv-SLIFMEM.