A multi core dynamic partial reconfiguration of FPGA for memory application

Abstract

The fault tolerance of Dynamic Partial Reconfiguration DPR model for fault tolerance system in asynchronous clock operation model in Field Programmable Gate Array FPGA using equalizer technique to reduce the faults and decreases the runtime and memory space is stored In partial reconfiguration PR based design circuits have larger devices more power consumption and less system upgradability with more memory space So to overcome this problem we propose a dynamic partial reconfiguration model for fault tolerance system in asynchronous clock operation mode The CPU usage of asynchronous system is reduced using DPR The wires of the worldwide routing channels have the delay of 2ns for the extension of every asynchronous island supported the interconnect wire delay of the Virtex 2 FPGA We propose a lossless image compression using dynamic partial reconfiguration model that creates a high level algorithmic language for expressing image compression and compiling them to FPGAs The compiler provides a one step compilation to host executable and FPGA configurations After parsing and type checking the compiler converts the program to a hierarchical Data Dependence and Control Flow DDCF representation based on the compression algorithm called modified SPIHT using 2D DWT The DDCF is used as a method of fault tolerance through dynamic partial reconfiguration for processor based Systems The configurable margin examine circuit decrease the examination time and accelerate the deficiency determination in Field Programmable Transistor Array FPTA and improve the unwavering quality of the Active Reconfiguration System ARS The binary record contains all the learning that decides the executed circuit similar to the qualities keep inside the Look up Tables LUTs beginning set and reset remaining of flip flops introduction esteems for recollections voltage detail of the Input Output I O sticks and steering data for the programmable interconnect to change the assets to make the portrayed circuit