Design and implementation of faithful approximate adders in digital image processing applications

Abstract

Advancement in contemporary high throughput communication newlineprotocols (such as 5G), has led to exponential increase in usage of batteryoperated newlineportable VLSI platforms. Significant amount of multimedia content newlinein wireless data traffic makes signal and image processing modules the most newlinepower bleeding part of VLSI signal processing platforms. Therefore, design newlineof efficient data path elements for signal and image processing applications newlinehas emerged as a significant research goal. As VLSI technology node reach newlinelow nanometre lengths, previously insignificant process variations are the newlineimportant design bottlenecks in modern VLSI signal processing systems. newlineAlso, minor gains in terms of hardware cost overhead in a small but newlinesignificant module can have a major impact on overall efficiency of VLSI newlinearchitecture. Failure of traditional circuit optimization approaches has given newlineway to unorthodox design techniques and algorithms that show excellent newlinetrade-offs between the quality of output and required computation resources. newlineApproximation Computing (AC) is one such technique that targets the dual newlineissue of handling error prone data and achieve acceptable area-power newlineoverhead of ASIC requirements. newlineSince adder blocks, are a vital part of any signal processing system, the newlinedesign of an adder plays a significant impact on energy consumption and area newlineof VLSI data path systems. Traditional exact adder algorithms restrained by newlinetheir preciseness , attain limited efficiency in terms of area, delay and power newlineconsumption. Significant gains achieved by various contemporary works on newlineapproximate adders built upon modified adder algorithms made a strong case newlinefor further exploration of approximate adder domain.