Design and implementation of a novel Serial transceiver using low power And high performance shift register

Abstract

Shift registers are the basic components in Very Large Scale Integration (VLSI) circuit design, which are used in various applications like communication transceivers, digital filters, cryptography circuits and network security devices. The expansion of word length in shift registers makes it appropriate for processing large scale data, since the data generated from various devices are of high quality one. Flip Flops (FFs) are the primary gadgets to integrate the shift register, where the numeral devices are interconnected with one other in series with respect to the register length. The data mobilization from input to output of the register is synchronized by the clock signal, which triggers the FFs either in rising or in falling edge. The performance of the shift register is prejudiced by key drivers such as area occupancy and energy consumption of the internal functional units. The former is determined by the number of devices and the later is done by several factors including unnecessary transistor switching, charge leakage and charge sharing due to unwanted parasitic components leading to both excessive static power and dynamic power consumption. The present study aims at the reduction of power expenditure and area possession of the shift registers by reconstructing their internal modules. In the proposed shift register the available FF topologies are reinstate with new Conditional Pass Logic Flip Flop (CPLFF) structures and the existing clock distribution system is replaced by power and area efficient clock pulse generator designed using multiplexer. newline